发明名称 Power modelling in circuit designs
摘要 A system and method is described for generating a power model of a circuit from a lower level description, such as Gate-level or RTL. In one aspect, simulation data is converted into a series of messages or transactions. Power is then determined on a per message or per transaction basis. In another aspect, an abstract power model is generated using a neural network. The neural network generates a system of weighted equations representing an accurate power model.
申请公布号 US2007276645(A1) 申请公布日期 2007.11.29
申请号 US20070811680 申请日期 2007.06.11
申请人 VELLER YOSSI;HANGA VASILE;ROZENMAN ALEXANDER;RACHAMIM RAMI 发明人 VELLER YOSSI;HANGA VASILE;ROZENMAN ALEXANDER;RACHAMIM RAMI
分类号 G06F17/50 主分类号 G06F17/50
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