发明名称 SEMICONDUCTOR MEMORY DEVICE AND ITS TEST METHOD
摘要 PROBLEM TO BE SOLVED: To set arbitrary operation mode information to a plurality of CR during a test and to reduce a test cost. SOLUTION: CR 112-1 to 112-3 hold operation mode information, when a CR control circuit 113 detects a wrote-in instruction or a read-out instruction for an address for register access in the prescribed order, updates operation mode information with time division for each CR, a command generation part 104a generates a test start instruction in which the write-in instruction, the read-out instruction, or write-in operation and read-out operation are not performed in accordance with a control signal from the outside, and generates again the test start instruction whenever CR is updated, and a data pad compression circuit 109 changes operation mode information written in the CR 112-1 to 112-3 by outputting reversing or leaving as it is test data input to a data pad of one part and making it data of a plurality of other data pads in accordance with a code expressed by a part of the input address when the test start instruction is sent out. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007310972(A) 申请公布日期 2007.11.29
申请号 JP20060140032 申请日期 2006.05.19
申请人 FUJITSU LTD 发明人 MORI IKU
分类号 G11C29/14;G01R31/28;G11C29/40 主分类号 G11C29/14
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