| 摘要 |
A phase locked loop for generating plural output signals is provided to generate plural PLL output signals which have an adjustable phase difference to a clock signal. A phase detector(PD) has an adjustable phase shifting device(30) for generating an adjusted phase-shifted version of an output signal of a phase locked loop, and a phase comparison device(32) for generating a phase detector output signal(PD_OUT) to determine a phase difference between the clock signal used and the adjusted phase-shifted version of the output signal. The adjusted phase-shifted version of the output signal is provided as a further output signal(CK) of the phase locked loop.
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