| 摘要 |
An address generator applied to a convolutional interleaver/deinterleaver generates an address for reading/storing data symbols from/to a memory. The memory conceptually divides into branches, segments and cells. The address generator maintains cyclic counters including a cyclic branch counter, a cyclic cell counter, N cyclic segment counters for counting the branch, segment and cell for generating the address. The address generator also comprising a processor generates an address according to the values of the cyclic branch counter, the cyclic cell counter, and N segment counters for indicating a memory cell for reading and storing data symbols.
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