发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To control either one performance of p-channel and n-channel transistors by using an STI stress, and to efficiently improve the performances of the p-channel and n-channel transistors in a CMOSLSI such as a gate array. SOLUTION: A semiconductor integrated circuit loads a CMOS circuit using an n-channel transistor and a p-channel transistor. In the semiconductor integrated circuit, elements are isolated by a gate-isolation structure in either one of the n-channel transistor and the p-channel transistor and by a shallow-trench isolation structure in the other. COPYRIGHT: (C)2008,JPO&INPIT
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申请公布号 |
JP2007311491(A) |
申请公布日期 |
2007.11.29 |
申请号 |
JP20060138019 |
申请日期 |
2006.05.17 |
申请人 |
TOSHIBA CORP;TOSHIBA MICROELECTRONICS CORP |
发明人 |
UCHINO YUKINORI;MAENO MUNEAKI;TAKEGAWA YOICHI;CHIKAMATSU NAOHITO |
分类号 |
H01L21/8238;H01L21/76;H01L21/82;H01L21/822;H01L27/04;H01L27/08;H01L27/092;H01L27/118 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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