| 摘要 |
PROBLEM TO BE SOLVED: To provide a forming method of an integrated circuit for reducing parasitic capacitance and a leakage current between adjacent conductive wiring, and an integrated circuit capable of reducing the parasitic capacitance and the leakage current between the adjacent conductive wiring. SOLUTION: An integrated circuit includes a semiconductor substrate, a low dielectric layer on the semiconductor substrate, a first groove in the low dielectric layer, and a first diffusion barrier layer covering the low dielectric layer in the first groove, so that the first diffusion barrier layer has a bottom connected to a side wall which has an upper side surface close to the upper side surface of the low dielectric layer. The integrated circuit further has conductive wiring with which the first groove is filled, and the conductive wiring has a surface lower than the upper side surface of the side wall of the diffusion barrier layer, and a metal cap is substantially directly formed only on an area on the conductive wiring. COPYRIGHT: (C)2008,JPO&INPIT
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