<p>Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.</p>
申请公布号
WO2007135077(A1)
申请公布日期
2007.11.29
申请号
WO2007EP54794
申请日期
2007.05.16
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED;DREPS, DANIEL;GOWER, KEVIN;MAULE, WARREN;TREMAINE, ROBERT
发明人
DREPS, DANIEL;GOWER, KEVIN;MAULE, WARREN;TREMAINE, ROBERT