发明名称 Stagger memory cell array
摘要 A memory device includes a first memory cell area having a first latch area where one or more electronic components are constructed for storing a value, and a first peripheral area surrounding the first latch area; and a second memory cell area being disposed adjacent to a first side of the first memory cell area, and having a second latch area where one or more electronic components are constructed for storing a value, and a second peripheral area surrounding the second latch area. One edge of the first memory cell area shifts away from its corresponding edge of the second memory cell area. Thus, the area or yield rate of the memory device can be adjusted.
申请公布号 US2007272985(A1) 申请公布日期 2007.11.29
申请号 US20060441646 申请日期 2006.05.25
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 HSIEH YEOU-LANG;HUANG CHING-KUN;SHEU JENG-DONG
分类号 H01L29/94 主分类号 H01L29/94
代理机构 代理人
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