| 摘要 |
A designing method of a semiconductor integrated circuit, by which a semiconductor integrated circuit with a small amount of wire routing, a small layout area and low wire capacitance can be achieved effectively. The designing method of the semiconductor integrated circuit of the invention has a logic synthesis step of generating a first netlist that defines the connection between standard cells stored in a cell library based on the specifications of the semiconductor integrated circuit, a cell composition step of analyzing the first netlist to extract a combination of standard cells, which satisfies predetermined criteria, of composing the extracted combination of standard cells to store it as a new standard cell in the cell library, and of rewriting the first netlist using the new standard cell to generate a second netlist, and a step of performing automatic placement and routing based on the second netlist.
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