| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a means capable of facilitating external monitoring of accesses from a control LSI to a high-speed memory. <P>SOLUTION: When the access waveform to a specific address of the high-speed memory 020 is observed out of the control LSI 010, an address of the waveform observation object is determined by an address comparison part 014, and when the address of the waveform observation object is generated as an access to the address of the high-speed memory 020, a bus trace signal switching part 014 is controlled by the address comparison part 014 and an AND gate 019 to connect a high-speed memory bus 017 to a low-speed memory bus 018. According to this, the access signal from a CPU 011 to the high-speed memory 020 is output out of the control LSI 0101 via the high-speed memory bus 017→the bus trace signal switching part 015→the low-speed memory bus 018, and the access state to the high-speed memory 020 can be thus observed on the low-speed memory side. <P>COPYRIGHT: (C)2008,JPO&INPIT |
