SELECTIVE UNIAXIAL STRESS RELAXATION BY LAYOUT OPTIMIZATION IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT

摘要

An integrated circuit (200) includes NMOS and PMOS transistors (220, 230). The NMOS (220) has a strained channel having first and second stress values along first and second axes respectively. The PMOS (230) has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS (220) and PMOS (230) have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/or width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS (220) may include multiple dielectric structures in the active layer underlying the gate. The SA of the PMOS (230) may be less than the SA of the NMOS (220). The integrated circuit may include a tensile stressor of silicon nitride over the NMOS (220) and a compressive stressor of silicon nitride over the PMOS (230).