| 摘要 |
935,293. Pulse code modulation systems; transistor pulse circuits. WESTERN ELECTRIC CO. Inc. Jan. 6, 1960 [Jan. 19, 1959], No. 479/60. Classes 40 (5) and 40 (6). The output of a transmitter 2 is applied to a coder 4 which provides a pulse coded output (a), Fig. 1, which is supplied to a binary counter 6 providing an output (b). A differentiator 8 is connected to the output of the counter 6, and provides an output (c) equivalent to that shown at (a) but with alternate positive pulses reversed in polarity. At the receiver the signal is converted into the original binary code pulse train (d) by a full-wave rectifier 12, decoded at 14, and supplied to a receiver 16. At the repeater 10 the signal is applied via a line equalizer 22, Fig. 4, to a three-stage transistor amplifier 28, 30, 32, provided with negative feedback via resistor 58. The output of the amplifier is supplied via a transformer 62, full wave rectifiers 70, 72, and a filter tuned to the basic pulse repetition frequency, to a " clock " amplifier 74 and the resulting positive clock pulses are applied to the cathodes of diodes 80, 82, which in the absence of clock pulses are forward biased by positive voltage 84. The signals at terminals 68, 66 are applied to the cathodes of diodes 86, 96, respectively, and the arrangement is such that the flip-flop 90, 94, changes state each time a positive clock pulse coincides with a positive pulse from terminal 66 or 68. The collector of transistor 94 is connected to one side of the primary winding of transformer 102, the collector of transistor 90 being connected to the other side, and oppositely poled pulses (c) appear across the secondary. The transformer may be of the saturating type. In alternative arrangements a pair of transistor blocking oscillators replace the flipflop circuit. Specification 865,353 is referred to. |
