| 摘要 |
A memory device for reducing the number of global lines is provided to reduce the number of total lines connected to a memory core by sharing a global input/output line. A memory device includes a plurality of memory banks, a global input/output line and a bank selection signal transfer unit(100). The global input/output line transfers a data input/output signal of the bank during a normal operation. The bank selection signal transfer unit transfers a plurality of test bank selection signals to the bank through the global input/output line in a core test mode to test a core region of the bank during a test operation. The bank selection signal transfer unit includes a transfer control signal generation unit(120) and a transfer unit(140,160,180).
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