发明名称 Method and apparatus for parallelly processing data and error correction code in memory
摘要 A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first syndrome based on the first data and the first ECC code, (2) correcting the first data according to the first syndrome, while reading the second data, and calculating the second syndrome based on the second data and the second ECC code, (3) and correcting the second data according to the second syndrome, while reading the third data and calculating the third syndrome based on the third data and the third ECC code.
申请公布号 US7299399(B2) 申请公布日期 2007.11.20
申请号 US20040842568 申请日期 2004.05.11
申请人 GENESYS LOGIC, INC. 发明人 HUANG CHE-CHI
分类号 H03M13/00;G06F11/10;G06F11/16;G06F13/00 主分类号 H03M13/00
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