| 摘要 |
Implementing maintenance of a higher speed with fewest possible additional circuits while suppressing deterioration in characteristics of a clock buffer caused by an offset voltage. In a clock buffer circuit comprising a differential amplifier including a pair of load resistances, a pair of differential stage transistors, a constant current source transistor for supplying an operating current to the differential stage transistors, and a bias circuit for supplying to the constant current source transistor a bias voltage according to the resistance value of the load resistances, the bias circuit generates the bias voltage so controlled that the voltage gain of the clock buffer circuit becomes a predetermined value with respect to a variation of the resistance value of the load resistances.
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