| 摘要 |
A semiconductor memory device is provided to enable the level of an internal voltage to arrive at a target level more easily in the end period of a driver, by controlling enable pulse width according to the internal voltage level. A pulse width control circuit(10) receives a first enable pulse having constant width generated by an active signal, and outputs a second enable pulse longer than the width of the first enable pulse according to the level of the internal voltage. A driver maintains the internal voltage as much as the voltage of a target level during an enable period of the second enable pulse by receiving the second enable pulse. The pulse width control circuit includes a voltage divider circuit(10-1), a delay circuit(10-2) and a pulse generation circuit(10-3). The voltage divider circuit decreases the internal voltage. The delay circuit determines delay time of the first enable pulse according to the level of the internal voltage. The pulse generation circuit generates the second enable pulse by receiving the first enable pulse and an output pulse of the delay circuit.
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