发明名称 Method of Manufacturing the Substrate for Packaging Integrated Circuits
摘要 A method of manufacturing a substrate for packaging ICs is disclosed, which coats a thin conductive layer on the bottom surface of the laminated circuit board, for electrically connecting the pad and the circuit pattern formed on the bottom surface after one line photolithography/etching step. The pad formed on the top surface of the laminated circuit board can be electrically connected to the power applied in the electroplating process through the electroplating layer in the through hole and the conductive layer. Hence, the times of line photolithography/etching steps required for the prior process can be reduced, thereby solving the issues of lowering yield caused by the line photolithography/etching steps.
申请公布号 US2007264750(A1) 申请公布日期 2007.11.15
申请号 US20060564003 申请日期 2006.11.28
申请人 ADVANCED SEMICONDUCTOR ENGINEERING INC. 发明人 TSENG CHI-CHAO
分类号 H01L21/00 主分类号 H01L21/00
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