| 摘要 |
A semiconductor memory device for reducing a layout area is provided to reduce a layout area of a feed cell by connecting electrically a first power line through a contact to a first well region. A memory array includes a plurality of memory cells arranged in a matrix and a plurality of feed cells. Each of the memory cells includes a pair of second conductive type load transistors formed in a first conductive type first well region and a pair of first conductive type diver transistors connected to the load transistors in order to form a flip-flop. Each of the power feed cells corresponds to each of memory cell columns and includes a row for feeding the first and second well regions. The first and second well regions are alternately disposed in a row direction in order to be extended in a column direction. A first power line is electrically connected to the feed cells in order to supply a first supply voltage to the first well region. A second power line is electrically connected to the feed cells in order to supply a second supply voltage to the second well region. The first power line is electrically connected through the feed cells to the first well region. The second power line is electrically connected through a plurality of contacts to the second well region. |
