| 摘要 |
A delay locked loop is provided to prevent malfunction of a circuit by outputting a normal signal by detecting jitter through a jitter detecting circuit in order to prevent dithering of a signal due to phase difference, and mixing the signals through signal inversion by a phase mixer. A delay locked loop(300) includes a clock buffer(310) generating an input clock(EXCLK) by synchronizing the falling or rising edge of external clocks(ECLK,ECLKB) in response to the external clock and an external invert clock; a coarse delay unit(320) outputting first and second coarse delay clocks(FCLK,SCLK) with different phases in response to a coarse delay control signal; a fine tuning unit(330) outputting a first mixing clock(MIX_CLK1) generated by mixing the first and second coarse delay clocks, or a second mixing clock(MIX_CLK2) generated by mixing the first mixing clock and an invert mixing clock generated by mixing the inverted first and second coarse delay clocks, in response to plural fine delay control signals(WTCTL); a replica delay unit(340) generating a feedback clock(FBCLK) by receiving the second mixing clock and reflecting a delay condition of the real clock path; a phase detector(350) generating a detection signal(PCTL) by comparing phases of the rising edges of the feedback clock and the input clock; a delay control unit(360) outputting the coarse delay control signal and plural fine delay control signals in response to the detection signal; and an output driver(370) outputting the second mixing clock as an output clock(OUTCLK). |
