| 摘要 |
PROBLEM TO BE SOLVED: To uniformize a system read latency of a memory device for the purpose of reducing complexity of a memory controller. SOLUTION: By a control circuit 2000, after receiving the flag signal by the control circuit, a memory device begins to output data associated with a previously received command onto at least one data signal line from a memory array in the predetermined number of read clock cycles, and the aforementioned number of read clock cycles is preliminarily determined according to a feature of signal propagation in order to equalize it to the read latency of the memory device. COPYRIGHT: (C)2008,JPO&INPIT
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