| 摘要 |
A multilayer parallel plate capacitor with an extremely low inductance comprises a generally rectangular parallelepiped that includes at least one pair of generally rectangular consecutive composite layers (40A, 40B) stacked parallel to each other in the vertical direction, each composite layer (40A, 40B) of the pair comprising a dielectric substrate (41A, 41B) and a conductor plate (42A, 42B) thereon. Each conductor plate (42A, 42B) includes two or more lead portions (45A, 45B) to enable connection to terminal electrodes, and plates (42A, 42B) on consecutive composite layers (40A, 40B) are connected to terminal electrodes of opposite polarity. Each conductor plate (42A, 42B) advantageously includes one or more non-conductive regions comprising slots (44Y) in the transverse direction, and one or more non-conductive regions comprising slots (44X) in the longitudinal direction. These slots (44X, 44Y) provide directionality to the electrical currents (47A, 47B) through the plates (42A, 42B), resulting in a capacitor structure with greatly reduced inductance.
|
