RECEIVER WITH CHIP-LEVEL EQUALISATION

摘要

The present invention relates to receiver apparatuses and methods of controlling weight adaptation in a receiver of a code multiplex telecommunications system with orthogonal spreading codes, wherein received discrete time signal samples are chip-level filtered by using a first equalising step. Additionally, the received discrete time signal samples are delayed by a time period corresponding to a data symbol and used in a second equalising step. Symbol estimates obtained from the first equalising step are non-linearly filtered and used as a desired response for the second equalising step in the following symbol period, wherein equaliser weights adapted in the second equalising step are used for the first equalising step. Alternatively, the second equalising step may be dispensed with and weight adaptation may be incorporated in a single equalising step. As an additional or alternative option, a hybrid equaliser architecture may be provided, where the above two-step equalisation is used during an active phase where a channel is allocated, while another weight updating scheme is used during an inactive phase where no channel is assigned. Thereby, detrimental effects of interference power can be reduced at low increase in complexity.