PROGRAMMABLE PROCESSOR ARCHITECTURE HIERARCHICAL COMPILATION

摘要

One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits or greater in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W . A scenario compiler is included in a hierarchical flow of compilation and used with other compilation and. assembler blocks to generate binary code based on different types of codes to allow for efficient processing based on the sub-processors while maintaining low power consumption when the binary code is executed.