发明名称 |
A router element for routing messages in a processing system |
摘要 |
<p>A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied. <IMAGE> <IMAGE></p> |
申请公布号 |
EP0757318(B1) |
申请公布日期 |
2007.11.14 |
申请号 |
EP19960304201 |
申请日期 |
1996.06.06 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
KRAUSE, JOHN C.;GARCIA, DAVID J.;HORST, ROBERT W.;ISWANDHI, GEOFFREY I.;SONNIER, DAVID PAUL;WATSON, WILLIAM JOEL;ZALZALA, LINDA ELLEN |
分类号 |
G06F11/18;G06F13/12;G01R31/317;G01R31/3185;G06F1/12;G06F9/52;G06F11/00;G06F11/10;G06F11/16;G06F11/20;G06F11/273;G06F12/08;G06F12/14;G06F12/16;G06F13/00;H04L12/46;H04L12/56;H04L29/14 |
主分类号 |
G06F11/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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