| 摘要 |
A semiconductor tester with features to facilitate testing of embedded memories. The circuitry allows tests to be generated algorithmically, but can be used in conjunction with scan test structures of semiconductor devices. Programming and debug time can be significantly reduced. The tester includes an algorithmic pattern generator that can generate a pattern for testing a memory. The tester also includes serializer circuits coupled to the algorithmic pattern generators that can convert the test pattern generated by the algorithmic pattern generator into one or more serial bit streams useful for scan testing an embedded memory. |
