发明名称 |
Apparatus and method for performing a load operation in a pipeline microprocessor |
摘要 |
<p>A pipeline microprocessor that distributes the instruction dispatching function between a main instruction dispatcher and dispatching logic within a plurality of execution units is disclosed. If the main instruction dispatcher requests load data from a data cache that indicates the data is unavailable, the instruction dispatcher provides to the appropriate execution unit the load instruction (without the load data), a tag (also known by the cache) uniquely identifying the unavailable data, and a false data valid indicator. The cache subsequently obtains the data and outputs it on a bus along with the tag. The dispatching logic in the execution unit is monitoring the bus looking for a valid tag that matches tags of entries in its queue with invalid data indicators. Upon a match, the dispatching logic obtains the data from the bus and subsequently dispatches the instruction along with the data to a functional unit for execution.
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申请公布号 |
EP1569090(A3) |
申请公布日期 |
2007.11.14 |
申请号 |
EP20040255566 |
申请日期 |
2004.09.14 |
申请人 |
VIA TECHNOLOGIES, INC. |
发明人 |
HOOKER, RODNEY E.;JOHNSON, DANIEL W.J.;LOPER, ALBERT J. |
分类号 |
G06F9/38;G06F9/00;G06F9/312 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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