| 摘要 |
The present invention relates to a circuit for phase/frequency detection, comprising a first and a second D-latch (22, 27) and a logic circuit (38). The first D-latch (22) comprises a data input terminal (23), which is coupled to a reference terminal (20), and a clock input terminal (24), which is coupled to an oscillator terminal (21). The second D-latch (27) comprises a data input terminal (28) coupled to the oscillator terminal (21) and a clock input terminal (29) coupled to the reference terminal (20). The logic circuit (38) comprises a first and a second input terminal which is connected to the first D-Latch (22) and to the second D-Latch (27) respectively and a first and a second phase detector terminal (34, 35) for providing a first and a second phase detector signal (Vup, Vdo) respectively. |
