| 摘要 |
Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed herein. Aspects of the method may comprise coupling a gate of a first transistor to a first differential input of the buffer and coupling a gate of a second transistor to a second differential input of the buffer. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer, where the common mode output of the DC voltage source may be coupled to the gate of the first transistor and the gate of the second transistor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.
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