发明名称 Memory management circuitry translation information retrieval during debugging
摘要 A system for obtaining translation information from a data processing system. The system includes circuitry for receiving an external request for translation information. The circuitry determines whether the requested translation information is present in memory management circuitry of a data processing system. If the translation information is not present in the memory management circuitry, the circuitry requests retrieval of the information by a processor core. In one embodiment, the request is performed by generating an interrupt to the processor core. In other embodiments, the request is preformed by requesting the activation of a program thread to be executed by the processor core.
申请公布号 US7296137(B2) 申请公布日期 2007.11.13
申请号 US20050140176 申请日期 2005.05.27
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 MOYER WILLIAM C.
分类号 G06F12/00;G06F9/45 主分类号 G06F12/00
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