| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an image decoding processing circuit capable of reducing the cost and increasing a decoding speed. <P>SOLUTION: The image decoding processing circuit 1 includes a reversible decoder 2, an inverse quantizer 3, an IDCT device 4, an adder 5, a deblock filter 6, a frame memory 7, and a motion estimator/compensator 8. The reversible decoder 2 subjects input data to variable length decoding processing. The inverse quantizer 3 performs inverse quantization of a transform coefficient. The IDCT device 4 subjects the transform coefficient to IDCT processing to generate a difference image and records this image in a recording part 10. Furthermore, the IDCT device 4 reads out several pixels corresponding an intra estimation mode out of several pixels adjacent to a block to be decoded, from the frame memory 7 to generate an estimated image and adds the generated estimated image to the differetial image recorded in the recording part 10. The adder 5 supplies a reproduced image to the deblock filter 6 as it is. The deblock filter 6 performs deblock filtering processing. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
