DATA PROCESSING APPARATUS

摘要

A universal asynchronous receiver-transmitter module (URM) comprises a sampling controller (CRC, CNT, FPC, SEL, SCF, FSM) that assigns a variable number of active edges in a clock signal (BCK) to respective bits in a serial data signal (SD). A serial data reception path (GF, RRG) derives a bit from the serial data signal on the basis of the variable number of active edges that the sampling controller has assigned to the bit.