DFT TECHNIQUES TO REDUCE TEST TIME AND POWER FOR SoCs

摘要

A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all flip-flops in the core. The partial residual test mode spans across a subset of the cores and allows to bound the number of cores that a full residual test mode may span across. The interaction of the cores among one another at the top-level is analyzed and the minimum number of flip-flops in a core that must participate in a intermediate test mode is selected. Algorithms are devised to analyze the interactions among the cores and build data structures which are used for identifying intermediate test modes. Using a reconfigurable scan segment architecture, intermediate test modes are implemented that are designed to work with all known test compression solutions. Since the length of the longest scan chain in an intermediate residual test mode is much smaller than the length of the longest scan chain in the full residual test mode, there is a substantial improvement in test application time as well as test peak power.