发明名称 |
Method and System for Preventing Noise Disturbance in High Speed, Low Power Memory |
摘要 |
A memory device comprises a memory cell and a sense amplifier which has a sensing interval. An output circuit is coupled to the sense amplifier and responsive to a clock signal to accept the signal from the sense amplifier. A first source of timing signals generates a first timing signal in response to an enable signal which is asynchronous relative to the clock signal. A second source of timing signals generates a second timing signal based on the clock signal. A switch selects one of the first and second timing signals at the timing signals for use to define pre-charge and sensing intervals for the sense amplifier. The first source of timing signals is selected during an interval of time corresponding to a clock latency, so that the timing signals define a sensing interval where transitions in the clock signal are outside of the sensing interval.
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申请公布号 |
US2007258304(A1) |
申请公布日期 |
2007.11.08 |
申请号 |
US20060381484 |
申请日期 |
2006.05.03 |
申请人 |
MACRONIX INTERNATIONAL CO., LTD. |
发明人 |
CHEN TI W.;SHIH YI T.;LIAO PEI H.;LIU HO H. |
分类号 |
G11C8/00;G11C7/02 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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