| 摘要 |
PROBLEM TO BE SOLVED: To provide a technology of stabilizing a time from the arrival of a trigger signal to a substantial data output start. SOLUTION: In this data generating apparatus, a memory 54 supplies parallel data according to a frequency division clock D_CLK. An address counter 52 gives the same address to the memory 54 until the trigger signal arrives and advances addresses when the trigger signal arrives. A hexadecimal counter 62 counts a clock CLK faster than the frequency division clock and the count is circulated by each period of the frequency division clocks. A trigger information latch 64 latches the count of the counter 62 when receiving the trigger signal and gives the latched count to an MUX 58. The MUX 58 selectively generates parallel data in 16 bits from parallel data in total 32 bits received at first and second input terminals I<SB>1</SB>, I<SB>2</SB>according to the latch count. A parallel serial conversion circuit 60 converts rearranged parallel data from the MUX 58 into serial data according to the clock CLK. COPYRIGHT: (C)2008,JPO&INPIT |
