发明名称 Memory built in self test circuit and method for generating a hardware circuit comprising the routing boxes thereof
摘要 A circuit and a method for performing a memory built in self test (MBIST) are provided. The circuit comprises a plurality of routing boxes and a test controller. The test controller provides test input signals to a plurality of embedded memory blocks, receives data output signals output by the memory blocks in response to the test input signals, and verifies the data output signal based on the test input signals. The routing boxes are placed to form a common bus between the test controller and the memory blocks to transmit the signals between the test controller and the memory blocks.
申请公布号 US2007260924(A1) 申请公布日期 2007.11.08
申请号 US20060403345 申请日期 2006.04.12
申请人 CHANG CHE-CHIANG;PAN JIAN-DAI 发明人 CHANG CHE-CHIANG;PAN JIAN-DAI
分类号 G06F11/00 主分类号 G06F11/00
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