| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a phase splitter which divides an input clock into multiple clock signals and minimizes a skew between the clock signals for a PVT change. <P>SOLUTION: This phase splitter inputs an external clock and generates a first internal clock and a second internal clock with a phase difference of 180°. This phase splitter also comprises a first buffer for buffering and outputting the external clock signal, an inverter for inverting and outputting the external clock signal, a second buffer for buffering the output signal in the inverter, a first interpolation signal generator for inverting and outputting the external clock signal and a second interpolation signal generator for inverting and outputting the output signal in the inverter. In addition, this phase splitter interpolates signals output from the first buffer and second interpolation signal generator to produce the first internal lock signal and interpolates those from the second buffer and first interpolation signal generator to produce the second internal clock, resulting in skew minimization via the splitter. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
