| 摘要 |
A level shifter circuit is provided to improve data processing rate by shortening pull-up time of a pull-up PMOS. A level shifter part(100) comprises a first NMOS and a second NMOS changing an input voltage into a higher voltage level than the input voltage and receiving input signals with opposite phases, and a first PMOS and a second PMOS receiving a high voltage through a source in common. Gates of the first PMOS and the second PMOS are connected with each other. A voltage control part(120-1,120-2) restricts Vgs of the first PMOS and the second PMOS as a voltage lower than a Vgs breakdown voltage of the first PMOS and the second PMOS. A voltage output part(160) comprises a third PMOS receiving an output voltage of the level shifter part and a third NMOS receiving the input voltage, and outputs a voltage by switching the third PMOS and the third NMOS. A pull-up time shortening part(140-1,140-2) shortens the time for the drain voltage of the first PMOS and the second PMOS to be charged with a high voltage, when the first PMOS and the second PMOS are turned on.
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