Hybrid Transistor Structure and a Method for Making the Same

摘要

A topography ( 40 ) is provided which includes a device having a transistor formed from a stack of semiconductor layers ( 42/46 ). The different semiconductor layers are spaced apart by a gate ( 60 ) and by support structures ( 48 ) comprising a material having different etch characteristics than the materials of the spaced apart semiconductor layers. The device includes a first transistor channel ( 76 ) within the upper semiconductor layer and, in some cases, further includes a second transistor channel within the lower semiconductor layer. The resulting hybrid transistor structure may be fabricated as one of a pair of CMOS transistors, the other of which may include the same configuration or a different configuration. A method for fabricating the hybrid transistor structure includes forming a gate structure surrounding a suspended portion ( 52 ) of an upper patterned semiconductor layer ( 53 ) and extending down to a surface of a lower semiconductor layer ( 42 ).