发明名称 Parallel bit interleaver for a wireless system
摘要 Systems and methods are provided to process wireless data packets. A method includes determining a subset of data bits to be processed at a wireless transmitter and employing a clock edge to store the data. The clock edge allows parallel mapping of at least two bits from the subset of data bits into an interleaver memory per a given clock edge. From the memory, other encoding and scrambling processes are applied before transmitting the data packets across a wireless network.
申请公布号 US2007258532(A1) 申请公布日期 2007.11.08
申请号 US20060416853 申请日期 2006.05.02
申请人 QUALCOMM INCORPORATED 发明人 BAI JINXIA;SUN THOMAS
分类号 H04L27/36;H04L5/12;H04L23/02 主分类号 H04L27/36
代理机构 代理人
主权项
地址