发明名称 System and method for mitigating memory requirements during MPE-FEC processing
摘要 A receiver is provided, which is adapted to receive MPE-FEC frames and to correct erroneous sections within a received MPE-FEC frame by detecting unreliable sections and storing in an erasure list ("ESL") table compressed data that includes the base address of each detected erroneous section, together with the respective section's size. The size of the ESL table may be fixed, or it may correlate, or dynamically change according to the actual number of detected erroneous sections. The data stored in the erasure list may then be forwarded to a decoder to correct erroneous sections. The erroneous sections may be detected by using CRC, and the decoder may be a Reed-Solomon decoder. If the application data table of the MPE-FEC is error-free (or full or errors), in which case the erasure structure list is empty (or full of errors), in which case the ensure structure list is empty (or full), this means that no FEC reception and error corrections are required, because there are no sections to correct in the first case and the decoder is incapable of correcting too many sections in the second case. Therefore, the receiving circuitry, or at least the decoder, may be disabled to save battery power.
申请公布号 GB2437900(A) 申请公布日期 2007.11.07
申请号 GB20070016902 申请日期 2006.02.12
申请人 SIANO MOBILE SILICON LTD 发明人 RONEN JASHEK;ROY OREN;ALON IRONI;DROR MEIRI
分类号 H04L1/00 主分类号 H04L1/00
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