Process for integrating a non-volatile memory cell into a HV CMOS process

摘要

A process is given which can integrate the production of an EEPROM cell into a CMOS process without deteriorating the oxide quality of the CMOS gate oxides. It proposed the EEPROM floating gate (PS1) and the covering intermediate dielectric (10) is formed first and protected with a silicon nitride layer (SN) before forming the gate oxide areas of the CMOS structure.