| 摘要 |
A pattern structure for monitoring a silicide process of a CMOS and a designing method thereof are provided to measure a variation of a resistance of the silicide process by forming a PN junction structure on a gate body. A gate poly is deposited on a silicon substrate(100). A surface of the substrate is rinsed by using a gate oxide rinsing process. A gate oxide film is formed on the surface of the substrate. The gate poly is patterned by using a photo etching process, such that a gate body(200) is formed. When a pattern is formed, n+ and p+ ions are implanted, while a portion of the pattern is blocked by using a blocking layer. The blocking layers are alternatively blocked, such that n+ and p+ implantation layers(210,220) are formed in the gate body. An activation thermal process is performed on the gate body, such that a poly body(300) and terminals are formed.
|
