Split L2 latch with glitch free programmable delay

摘要

A programmable delay circuit that delays the C 2 clock signal by a variable amount that allows the output from the L 1 latch to be captured even when there is a large delta between the L 1 latch and its L 2 latch. This allows the C 2 signal to be adjusted within the system dependent upon the amount of cycle steal is needed. The C 2 clock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed C 2 is controlled to maintain a constant C 2 duty cycle.