| 摘要 |
A delay line, an analog-to-digital converting device and a load-sensing circuit using the same are provided. The delay line comprises a delay-control terminal, a reset terminal, and n delay cells DCELL<SUB>x </SUB>(0<x<=n). The delay cells DCELL<SUB>1</SUB>~DCELL<SUB>n </SUB>are connected in series to each other. Each of the delay cells DCELL<SUB>x </SUB>is coupled to the delay-control terminal and the reset terminal for transmitting the first level stage by stage between the delay cells according to a delay time decided by the delay-control terminal in a sensing period. The outputs of all delay cells are reset to the second level when the sensing period is finished. The sensing period is decided by the signal from the reset terminal. Wherein, at least an output terminal t<SUB>y </SUB>(0<y<=n) of a delay cell DCELL<SUB>y </SUB>among the delay cells DCELL<SUB>1</SUB>~DCELL<SUB>n </SUB>used as output terminal of the delay line.
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