A DATA ALIGNMENT CHIP FOR CAMERA LINK BOARD

摘要

A data alignment chip for a camera link board is provided to improve a consumed power and a processing speed and to easily configure a PCB layout by arranging data without a separate memory. A data alignment chip for a camera link board includes a clock generating unit(128), an address and control signal generating unit(126), a data converting unit(122), a data alignment unit(124), a dual port buffer(130) and a data bus multiplexer unit(132). The clock generating unit generates a reference operation signal clock of the data alignment chip by compensating for 'STROBE' and 'LVAL' signals among signals output from a camera link chip(114). The address and control signal generating unit generates an assignment number of the dual port buffer and an address signal for read/write. The data converting unit converts pixel data of CCD among signals output from the camera link chip into bit data. The data alignment unit aligns the data converted by the data converting unit according to a physical arrangement of the CCD and outputs the converted data. The dual port buffer stores the aligned data on the basis of the address signal and outputs the stored data. The data bus multiplexer unit outputs an output of the dual port buffer to one output port.