发明名称 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF EXECUTING HIGH-SPEED READ
摘要 A plurality of memory cells are arranged in a memory cell array. The plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines. A plurality of source lines are disposed along the plurality of bit lines. The plurality of source lines are connected respectively to sources of the plurality of memory cells at a time of data read.
申请公布号 US2007253272(A1) 申请公布日期 2007.11.01
申请号 US20070737413 申请日期 2007.04.19
申请人 SHIBATA NOBORU 发明人 SHIBATA NOBORU
分类号 G11C8/00 主分类号 G11C8/00
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