发明名称 |
PILLAR CELL FLASH MEMORY TECHNOLOGY |
摘要 |
An array of a pillar-type nonvolatile memory cells ( 803 ) has each memory cell isolated from adjacent memory cells by a trench ( 810 ). Each memory cell is formed by a stacking process layers on a substrate: tunnel oxide layer ( 815 ), polysilicon floating gate layer ( 819 ), ONO or oxide layer ( 822 ), polysilicon control gate layer ( 825 ). Many aspects of the process are self-aligned. An array of these memory cells will require less segmentation. Furthermore, the memory cell has enhanced programming characteristics because electrons are directed at a normal or nearly normal angle ( 843 ) to the floating gate ( 819 ).
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申请公布号 |
US2007252192(A1) |
申请公布日期 |
2007.11.01 |
申请号 |
US20070775808 |
申请日期 |
2007.07.10 |
申请人 |
MOKHLESI NIMA;LUTZE JEFFREY W |
发明人 |
MOKHLESI NIMA;LUTZE JEFFREY W. |
分类号 |
H01L29/788;G11C16/04;H01L21/336;H01L21/8247;H01L27/115;H01L29/423 |
主分类号 |
H01L29/788 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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