发明名称 |
Clock distribution circuit |
摘要 |
A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.
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申请公布号 |
US2007252631(A1) |
申请公布日期 |
2007.11.01 |
申请号 |
US20060414766 |
申请日期 |
2006.04.28 |
申请人 |
KAVIANI KAMBIZ;CHIN TSU-JU |
发明人 |
KAVIANI KAMBIZ;CHIN TSU-JU |
分类号 |
G06F1/04 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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