| 摘要 |
A memory (10) includes a plurality of memory arrays. Each of the plurality of memory arrays includes a plurality of sub-arrays (52-129). A plurality of power supply conductors (158, 160) are provided over the memory (10) for supplying power to the plurality of memory arrays. When accessing the memory (10) to simultaneously read a plurality of bits from the memory (10), the sub-arrays (52, 129) are accessed so as to provide a relatively uniform current demand on the plurality of power supply conductors. In one embodiment, the accessed sub-arrays (52, 129) are organized so that sides, or edges, of each accessed sub-array are not adjacent to each other. |
