发明名称 |
METHOD FOR DESIGNING WIRING STRUCTURE OF LSI |
摘要 |
PROBLEM TO BE SOLVED: To provide a method for designing the wiring structure of an LSI in which the wiring capacitance C and the wiring delay RC can be reduced. SOLUTION: In a wiring structure having the wiring length of 1 mm or longer, permittivity of an inter-wiring insulation layer in the widthwise direction of wiring is set higher than the permittivity of the inter-wiring insulation layer in the thickness direction of wiring. COPYRIGHT: (C)2008,JPO&INPIT |
申请公布号 |
JP2007288216(A) |
申请公布日期 |
2007.11.01 |
申请号 |
JP20070167024 |
申请日期 |
2007.06.25 |
申请人 |
TOSHIBA CORP |
发明人 |
SHIGYO NAOYUKI;YAMAGUCHI TETSUYA |
分类号 |
H01L21/768;H01L21/3205;H01L21/82;H01L21/822;H01L23/52;H01L23/522;H01L27/04 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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